1. Field of the Invention
The present invention relates to a bidirectional signal control circuit, and particularly to a bidirectional signal control circuit for controlling the transfer of data signals outputted from a plurality of tri state drivers through a wire used for bidirectional signals.
2. Description of the Related Art
Upon the design of an LSI, a plurality of functional blocks are placed over one chip and an interconnection or wire is used to connect between the functional blocks. It is common that designed blocks registered in a library are placed and a wire for transferring unidirectional or bidirectional signals is used to connect between the blocks. Such a semiconductor integrated circuit needs a high-speed operation. Therefore, it is also necessary to contrive the wire.
FIG. 2 is a diagram showing connections for transferring bidirectional signals, which are employed in a conventional semiconductor integrated circuit.
In FIG. 2, reference numeral 10 indicates an interconnection or wire for transferring bidirectional signals, which is employed in the semiconductor integrated circuit. Reference numerals 11, 12, 13, 14 and 15 respectively indicate tri state drivers placed at output lines for outputting signals to the wire 10.
The tri state drivers 11 through 15 are CMOS tri state drivers respectively. Each of the tri state drivers 11 through 15 has three output states: a normal 1 level (voltage level being a source voltage level), a normal 0 level (voltage level being a ground voltage level) and a high impedance state produced by electrically cutting off an output. Reference numerals 11a through 15a indicate control signals for controlling the tri state drivers 11 through 15, respectively.
When the semiconductor integrated circuit is a logic LSI, for example, the output lines electrically connected to the wire 10 used as a signal line via the tri state drivers 11 through 15 are called xe2x80x9cbus linesxe2x80x9d. Further, each of them is used so as to control the other gate to ┌high impedance┘ when logic of ┌0┘ or ┌1┘ is outputted to one gate. Since the logic LSI can be simplified in configuration when the tri state drivers 11 through 15 are used with respect to the output lines connected to the wire 10, it has been widely used.
However, with recent advances in scale down of a semiconductor integrated circuit, a delay due to load capacity and resistance, which results from a wiring length, becomes predominant. This RC wiring delay rapidly increases as compared with a gate delay. Thus, the transfer of bidirectional signals under the configuration shown in FIG. 2 has created difficulties in activating the semiconductor integrated circuit at high speed. Therefore, a block-to-block connection has been used in which buffers are interposed at midpoint in a wire as shown in FIG. 3.
FIG. 3 is a diagram showing an example illustrative of connections between bidirectional signals in an improved semiconductor integrated circuit. The same elements of structure as those shown in FIG. 2 are identified by the same reference numerals.
Referring to FIG. 3, reference numerals 21, 22, 23 and 24 respectively indicate bidirectional buffers placed in the course of an interconnection or wire used for the bidirectional signals. Reference numeral 30 indicates the wire used for the bidirectional signals. The wire 30 is divided into five wiring parts or sections 31, 32, 33, 34 and 35 by the bidirectional buffers 21 through 24 respectively.
Further, reference numerals 11, 12, 13, 14 and 15 respectively indicate tri state drivers respectively placed at output lines electrically connected to their corresponding wiring sections 31 through 35. Reference numerals 11a through 15a respectively indicate control signals for respectively controlling the directions of the tri state drivers 11 through 15 and the bidirectional buffers 21 through 24. Reference numerals 41 through 46 indicate OR gates for ORing the corresponding control signals 11a through 15a for the purpose of performing directional control and outputting the results of ORing to the bidirectional buffer 21 through 24 as control signals, respectively.
The bidirectional buffers 21 through 24 amplify the signals inputted thereto lying over the wiring sections 31 through 35 used for the bidirectional signals and supply the so-amplified signals to the adjacent wiring sections respectively. Incidentally, the bidirectional buffers might be called xe2x80x9crepeatersxe2x80x9d respectively. Further, tri state buffers might be called simply xe2x80x9cbuffersxe2x80x9d respectively.
When, for example, a signal is outputted to the wire 30 from the tri state driver 12 in the above-described configuration, the control signal 12a to be outputted to the tri state driver 12 is supplied thereto. Therefore, the bidirectional buffer 21 outputs the signal from the wiring section 32 to the wiring section 31, the bidirectional buffer 22 outputs the signal from wiring section 32 to the wiring section 33, the bidirectional buffer 23 outputs the signal from the wiring section 33 to the wiring section 34, and the bidirectional buffer 24 outputs the signal from the wiring section 34 to the wiring section 35, respectively. The signal is transferred in this way.
In such a conventional bidirectional signal control circuit, however, the signal lines for respectively supplying the control signals to the bidirectional buffers 21 through 24 respectively reach about ⅘ of the length of the wire when they are the longest. Therefore, a delay of each output control signal on the signal line for supplying the output control signal could lead to a hindrance to speeding up even if the speeding up of the transfer of each signal to the wire would be implemented. Thus, a problem arises in that a further speeding-up is difficult.
An object of the present invention is to provide a bidirectional signal control circuit capable of reducing a delay of a control signal outputted from each of bidirectional buffers and achieving the speeding-up thereof in a simple configuration.
In order to solve the above problems, there is provided a bidirectional signal control circuit according to the present invention, which comprises a wire for transferring bidirectional signals, which is comprised of a plurality of sub line segments grouped into a first group including one or plural sub wires close to one another, a second group including the remaining sub line segments, and sub line segments placed between the first group and the second group; a plurality of drivers respectively connected to corresponding ones of the sub line segments and for respectively transferring data signals to the sub line segments in response to one of a plurality of control signals; and a plurality of bidirectional buffers respectively placed between the sub line segments. The bidirectional buffers connected to the sub line segments included in the first group are respectively controlled so as to transfer signals in the direction of the sub line segments placed between the first group and the second group when the data signals are respectively transferred to the sub line segments included in the fist group through the drivers. The bidirectional buffers connected to the sub line segments included in the second group are respectively controlled so as to transfer signals in the direction of the sub line segments placed between the first group and the second group when the data signals are respectively transferred to the sub line segments included in the second group through the drivers.
The object of the present invention is achieved by constructing the bidirectional signal control circuit in this way.